In clock generation circuits such as a CDR circuit and a DLL circuit, a phase comparator has been broadly used for making phase comparison between input data and a clock. As typical phase comparators well known are: a Hogge type which outputs a linear signal in accordance with a phase difference between two input signals (see Non-patent Document 1); and an Alexander type which just determines whether one input signal is advanced or delayed with respect to the other input signal, and outputs a binary signal (see Non-patent Document 2).
In the linear phase comparator typified by the Hogge type, for example as shown in FIG. 9, an output signal, whose value linearly changes in proportion to a phase difference between two input signals, is obtained. A phase detection range is generally a range from −π to +π, and the phase detection range characteristically returns in a 2π cycle.
FIG. 10 is a constitutional diagram of a case where the phase comparator is used for a DLL circuit. This DLL circuit has a closed loop made up of a linear phase comparator 11A, a charge pump 20, a low-pass filter 30, and a variable delay buffer (VCDL) circuit 40. A negative feedback is then applied such that a phase of a rising edge of a reference clock CLK1 inputted from the outside matches a phase of a rising edge of a feedback clock CLK2 outputted from the variable delay buffer circuit 40, namely the feedback clock CLK2 comes into the state of being delayed from the reference clock CLK1 just by one cycle (2π).
The variable delay buffer circuit 40 includes cascade-connected four-stage delay elements 41, 42, 43, 44 with same characteristics, and a common current source 45 for supplying an operating current to each of the delay elements 41 to 44. The current of the current source 45 is increased or decreased by means of an output signal of the low-pass filter 30, thereby to mutually control a delay amount of each of the delay elements 41 to 44. When the feedback clock CLK2 is delayed just by one cycle and the DLL circuit is locked, a delay clock PH1 delayed from the reference clock CLK1 just by ¼ cycle is obtained from the delay element 41 of the variable delay buffer circuit 40, a delay clock PH2 delayed just by 2/4 cycle is obtained from the delay element 42, and a delay clock PH3 delayed just by ¾ cycle is obtained from the delay element 43. A clock PH0 is the same clock as the reference clock CLK1, and a clock PH4 is the same clock as the feedback clock CLK2.